----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:26:08 12/06/2006 
-- Design Name: 
-- Module Name:    UART_top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity UART_top is
    Port ( clk : in  STD_LOGIC;
			  sw : in std_logic_vector (7 downto 0);
			  clk_out : out std_logic;
			  TX_en : out std_logic;
           Tx : out STD_LOGIC;
			  Tx1 : out STD_LOGIC);
end UART_top;

architecture Behavioral of UART_top is

signal clk0 : std_logic;
signal clk24 : std_logic;
signal clkin_IBUFG_out : std_logic;

signal clk96 : std_logic;
signal clk_counter : integer range 0 to 1250;

signal tx_counter : integer;
signal delay_counter : integer;
signal tx_data : std_logic;

signal tx_enable : std_logic;

signal data : std_logic_vector(7 downto 0) := X"00";

begin

clk_out <= clk96;

data <= sw;

Tx <= tx_data;
Tx_en <= tx_enable;
Tx1 <= tx_data;

clock_9600Hz : process(clk24)
begin
	if rising_edge(clk24) then
		if clk_counter = 1250 then
			clk96 <= not clk96;
			clk_counter <= 0;
		else
			clk_counter <= clk_counter + 1;
		end if;
	end if;
end process clock_9600Hz;

process(clk96)
begin
	if rising_edge(clk96) then
		if delay_counter = 1008 then
			delay_counter <= 0;
			tx_counter <= 0;
		else
			delay_counter <= delay_counter + 1;
			if delay_counter >= 1000 then
				tx_counter <= tx_counter + 1;
			end if;
		end if;
	end if;
end process;

process(clk96)
begin
	if rising_edge(clk96) then
		if tx_counter > 0 then
			tx_enable <= '1';
		elsif tx_counter = 0 then
			tx_enable <= '0';
		end if;
	end if;
end process;

UART_Tx : process(clk96)
begin
	if rising_edge(clk96) then
		if delay_counter < 1000 then
			tx_data <= '1';
		elsif delay_counter >= 1000 then
			if tx_counter = 0 then
				tx_data <= '0';
			elsif tx_counter > 0 then
				tx_data <= data(tx_counter-1);
			end if;
		end if;
	end if;
end process UART_Tx;


clock_24MHz: entity work.clk24M
port map( CLKIN_IN        => clk,
          RST_IN          => '0',
          CLKFX_OUT       => clk24,
          CLKIN_IBUFG_OUT => clkin_IBUFG_out,
          CLK0_OUT        => clk0);

end Behavioral;

